Topic: “Cloud and Computing Architecture“
About this Event
Agenda
1:00 ~ 1:05: Ganping Ju (CAISS President) – “CAISS 2020 introduction”
1:05 ~ 1:45: Speaker 1 – Jason Adrian, “Optimizing Flash Form Factors and Magnetic Storage Performance for the Cloud” (30 mins presentation + 10 mins Q&A)
1:45 ~ 2:25: Speaker 2 – Andy He, “The Importance of High-speed Interconnect in the Computing Architecture” (30 mins presentation + 10 mins Q&A)
2:25 ~ 2:40: 2 speakers + 2 BOA members – “Panel discussion”
Speaker 1: Jason Adrian
Principal Hardware Architect – Azure Storage Hardware at Microsoft.
Jason is a storage hardware architect at Microsoft Azure, defining the technologies and system designs that power one of the world’s largest cloud storage fleets. Jason is passionate about hyper-scale and scale-out storage systems and storage architectures. His experience ranges from high-performance flash systems to archival systems, and everything in between. Jason was previously a hardware systems engineer at Facebook, a storage hardware architect at Dell, and a design engineer at EMC. He has 36 granted patents.
Topic: “Optimizing Flash Form Factors and Magnetic Storage Performance for the Cloud”
SSDs have gone from expensive storage devices used sparingly to a main-stream storage solution. In this transition, SSDs have left behind the legacy HDD defined form factors and are finding more optimal design opportunities including E1.S/L and E3.S/L. With E1.L SSDs, we can enable designs that can fit 1PB of flash in a front-serviceable system in the near future! On the other hand, E1.S SSDs can enable very high-performance devices at a smaller capacity point that can be used across the storage and compute fleet. Together with the OCP community, we are working to ensure that an E1.S form factor is able to meet the needs of hyperscale consumers like us as well as the rest of the industry. We believe that these EDSFF form factors are the future of flash, and will optimize and unlock new opportunities in our system designs.
In the magnetic storage realm, HDDs continue to increase in capacity but the IOPS/TB doesn’t. New technologies such as dual actuators are one way to solve the problem, but not the only solution. In this talk, we will talk about industry trends and opportunities to leverage the largest HDDs available on the market.
Speaker 2: Andy He
Chip Technologist & IP Lead @ Google
Andy He is currently Chip Technologist & IP Lead at Google, working on the next generation of TPU design and technology. Previously he was a senior engineering manager at Nvidia, leading GDDR & HBM memory hardware and architecture design used in all GPU products at Nvidia. He has 10+ years’ experience in the architecture, design, and management of various technologies used in GPU and DSA (domain-specific accelerator). He holds an MBA from UC Berkeley and MS from the University of Southern California.
Topic: “The importance of high-speed interconnect in the computing architecture”
As the GPU and DSA (domain-specific accelerator) become more and more popular in various AI and HPC applications, including autonomous driving, data center training/inference, and robots, more and more efforts have been spent on increasing the performance and energy efficiency of these platforms. High speed interconnects in the processor and infrastructure have thus become one of the bottlenecks of achieving this goal in the corresponding hardware and system. This talk will examine the importance of this technology and its future development.
Location
Online Event
Please use the link to register