Program and Agenda
“Data Storage and More”
As great innovations and developments continue on applications, services, products enabled by Mobile Internet, the information storage society is also facing new challenges it brings. How to effectively obtain data; how to effectively turn disorganized data into useful information like behavior predictions; how to achieve efficient storage, and to structure the storage network, allocate network bandwidth and storage capacity; these are all important technological aspects of the future of Mobile Internet. In this year’s CAISS Annual Conference, industry leaders will get together to discuss technology challenges and possible solutions.
Date: October 15th, 2017 (Sunday)
Time: 2:30 PM – 8:00 PM
Venue: Computer History Museum, 1401 North Shoreline Boulevard, Mountain View, CA 94043
2:30PM – 3:00PM Registration & Networking
3:00PM – 3:15PM CAISS Updates: Dr. Yang Han, CAISS President
Dr. Lijie Guan, CAISS President-Elected 2018
3:15PM – 3:45PM Government official speech
3:45PM – 4:30PM Keynote Speech: H.-S. Philip Wong, Professor, Stanford University
4:30PM – 4:35PM Break and Raffle
4:35PM – 5:20PM Keynote Speech: Ravi Rajamani, Principal Strategy Advisor, Google Cloud
5:20PM – 6:05PM Keynote Speech: Chenwei Yan, VP and GM of Connected Products, Intel
6:05PM – 6:15PM Break and Raffle
6:15PM – 8:00PM Dinner Banquet
MC: Ms. Ziduan Zhang
Reaching for the N3XT 1,000× of Computing Energy Efficiency
21st century information technology (IT) must process, understand, classify, and organize vast amount of data in real-time. 21st century applications will be dominated by memory-centric computing operating on Tbytes of active data with little data locality. At the same time, massively redundant sensor arrays sampling the world around us will give humans the perception of additional “senses” blurring the boundary between biological, physical, and cyber worlds. Abundant-data processing, which comprises real-time big-data analytics and the processing of perceptual data in wearable devices, clearly demands computation efficiencies well beyond what can be achieved through business as usual. Computer architecture is going to change in the coming decade because today’s architecture has severe limitations in energy efficiency and latency for memory access.
The key elements of a scalable, fast, and energy-efficient computation platform that may provide another 1,000× in computing performance (energy-execution time product) for future computing workloads are: massive on-chip memory co-located with highly energy-efficient computation, enabled by monolithic 3D integration using ultra-dense and fine-grained massive connectivity. There will be multiple layers of analog and digital memories interleaved with computing logic, sensors, and application-specific devices. We call this technology platform N3XT – Nanoengineered Computing Systems Technology. N3XT will support conventional computing architectures as well as computation methods that embrace sparsity, stochasticity, and device variability, including those that are neuromorphic and learning-based.
In this talk, I will give an overview of nanoscale memory and logic technologies for implementing N3XT. I will survey the “new” memory technologies that are being explored currently in industry and in academia: spin-transfer torque magnetic memory, resistive switching metal oxide memory, conductive bridge memory, phase change memory. The eventual introduction into mass production will require detailed characterization and physical understanding of the non-idealities of these “new” memories, and development of techniques and technologies to overcome these non-idealities.
Dr. H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering. He joined Stanford University as Professor of Electrical Engineering in September, 2004. From 1988 to 2004, he was with the IBM T.J. Watson Research Center.
At IBM, he held various positions from Research Staff Member to Manager and Senior Manager. While he was Senior Manager, he had the responsibility of shaping and executing IBM’s strategy on nanoscale science and technology as well as exploratory silicon devices and semiconductor technology.
Professor Wong’s research aims at translating discoveries in science into practical technologies. His works have contributed to advancements in nanoscale science and technology, semiconductor technology, solid-state devices, and electronic imaging.
He is a Fellow of the IEEE. He served as the Editor-in-Chief of the IEEE Transactions on Nanotechnology (2005 – 2006), sub-committee Chair of the ISSCC (2003 – 2004), General Chair of the IEDM (2007), and is currently the Chair of the IEEE Executive Committee of the Symposia of VLSI Technology and Circuits. He is the faculty director of the Stanford Non-Volatile Memory Technology Research Initiative (NMTRI), and is the founding Faculty Co-Director of the Stanford SystemX Alliance – an industrial affiliate program focused on building systems.
Trends in enterprise storage architectures
Introduction to Google Cloud, Key enterprise use cases, Cloud differentiation and how enterprises can unlock value with new application architectures.
Mr. Ravi Rajamani is a seasoned IT Professional with exceptional knowledge of the enterprise data center infrastructures and software architectures from diverse experiences at Cisco, Oracle, NetApp and Sun Microsystems. He is currently a Principal Strategy Advisor at Google and is responsible for the Cloud platform adoption at enterprise customers in High Tech Manufacturing, Social Media and IOT. Prior to Google, Ravi was Director, Global Cloud Solutions at Cisco where he created and grew the Cloud business at key Enterprise, Federal and Service Provider customers. As a senior executive, Ravi led a team of architects and consultants to help enterprise customers design, develop and deploy automation of technology and business processes across the entire IT life cycle. He is an industry visionary in the areas of Cloud & Automation and is invited to speak at industry conferences such as Cisco Live, Oracle Openworld and user groups.
Ravi earned his MBA from the Haas School of Business, University of California, Berkeley (Go Bears!) and Masters in Systems Engineering from the University of Maryland, College Park. He is an avid fan of tennis, cricket and spends time coaching softball in recreational leagues. Ravi lives in Cupertino, CA with his wife and two daughters.
5G Challenges and Vision
5G will transform how we experience the world and how we do business and 5G marks an historic inflection point for the industry. Fundamental changes in the cloud, networks, storage, and devices will need to take place starting now to realize the potential of 5G:
- We are entering an entirely new era in which data computing will be distributed across the entire network from device to cloud, delivering more personalized and immersive experiences.
- A network and storage transformation will be required to meet the diverse speed, latency, energy and scale requirements in order to connect these billions of smart devices.
- The heterogeneous networks of 5G will be powerful, agile and flexible—built with a virtualized core and intelligent edge services.
- There will be an explosion of smart devices designed to connect to distributed cloud resources using a new range of radio access technologies, which will also have a profound Impact on storage solutions.
In today’s presentation, I will talk about how Intel is leading the 5G transformation. From product innovation to market leadership, Intel is investing in key networking, cloud & client technologies. 5G is happening now – in the network, the cloud and the client. As mobility evolves beyond the smart phone, 5G is becoming one of the most impactful technology transformations we are likely to see in our lifetime. It will deliver next-generation experiences including autonomous driving, smart cities, the Internet of Things, and, of course, the era of machines. Intel is uniquely positioned in its ability to power 5G cloud-to-client solutions:
- Intel has made early investments in cloud and core networks, radio technologies and compute platforms. We are bringing leading 5G connectivity technologies and solutions to market, from trial platforms to new modem technologies.
- Intel has a leading modem roadmap to support mobile clients with a wide range of client connectivity options for 4G and 5G.
- The company is pioneering efforts in several technologies that will enable next-generation core and access network. Innovation on the core network is crucial to support not only the increased data traffic, but also the diverse delivery needs of the myriad of new uses 5G will enable.
- Intel is also providing optimized software critical to ensure end-to-end compatibility, interoperability and optimization for greater speed and reduced latency.
Chenwei Yan is vice president in the Client Computing Group and the general manager of connected products and programs at Intel Corporation. He is responsible for product strategy and roadmap planning for Intel’s connected products and programs at key customers.
An accomplished leader, Yan has more than two decades of tech industry experience, working in both the United States and China. He joined Intel in 2017 with a breadth of expertise spanning sales, marketing, product management, operations and engineering. Most recently, Yan was vice president of sales and product marketing at Qualcomm Inc., based primarily in Shenzhen, China. He was responsible for Qualcomm’s chipset business in China, including solution sales, go-to-market strategy and product portfolio planning for smartphones and the emerging Internet of Things. Before joining Qualcomm in 2010, Yan spent two years as chief operating officer of VIA Telecom Inc., a semiconductor and mobile phone design company. Earlier in his career, he led wireless business unit operations at UTStarcom Inc. and served as a product manager for cable and wireless networking equipment at 3Com Corp. Yan started his career as a systems engineer at Rockwell International Corp. and Motorola Inc.
Yan holds a bachelor’s degree in computer and electrical engineering from Purdue University, a master’s degree in electrical engineering from Stanford University and an MBA degree from the University of Chicago.